1. Field of the Invention
The present invention relates to a structure of a storage device. In particular, the present invention relates to a structure of a folded dynamic RAM (dynamic random access memory: DRAM).
2. Description of the Related Art
The cost for a DRAM that is a storage device has been lowering; to further lower the cost, an increase in capacity has been actively researched and developed. The increase in capacity can be achieved by, for example, changing the layout of the memory cell and miniaturizing the element, but such a scale down of the dimension of the memory cell or reduction in the size of the element is limited.
In terms of the layout change of a memory cell, either an open bit-line architecture or a folded bit-line architecture may be adopted. The open bit-line architecture enables a scale down of the dimension of the memory cell but is weak against noise at the time of data reading. On the other hand, the folded bit-line architecture is strong against noise at the time of data reading, but it is difficult to scale down the dimension of the memory cell with the folded bit-line architecture. The reason why the folded bit-line architecture is strong against noise at the time of data reading is because a first bit line (reading bit line) and a second bit line (reference bit line), which are connected to a sense amplifier, are overlapped with the same word line, whereby noise attributed to the signal of the word line is superimposed equally on them to be cancelled.
Further, as another approach for the layout change of a memory cell, its elements may be stacked in a three-dimensional manner to scale down the dimension of the memory cell, as described in Patent Document 1 and Patent Document 2.